Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.Peer reviewe

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture

Circuit implementation of piecewise-affine functions based on lattice representation

This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to implement the lattice approach can be obtained by an off-line preprocessing that can be automated. Other advantages of the proposal are that it implements a continuous PWA function with potentially no errors and the minimum number of parameters to store. This has been proven experimentally by implementing the proposal in a Xilinx FPGA and comparing its performance with other implementations, all of them addressing a typical non linear control problem.Comunidad Europea FP7-IST-248858Ministerio de Ciencia e Innovación TEC2008-04920 y DPI2008-03847Junta de Andalucía P08-TIC-0367

Dedicated hardware IP module for extracting singular points from fingerprints

In this paper a new digital dedicated hardware IP module for extracting singular points from fingerprints is presented (in particular convex cores). This module comprises four main blocks that implement an image directional extraction, a smoothing process, singular point detection and finally, a post processing to obtain the exact location of the singular point. A Verilog HDL description has been developed for this solution. The description has been synthesized and implemented in FPGAs from Xilinx

Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems

Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices.European Union 952622Ministerio de Ciencia e Innovación PID2020-116664RB100, 10.13039/50110001103

VLSI Design of Trusted Virtual Sensors

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time)Ministerio de Economía, Industria y Competitividad TEC2014-57971-RConsejo Superior de Investigaciones Científicas 201750E01

Digital implementation of hierarchical piecewise-affine controllers

This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing.Comunidad Europea FP7-IST-248858Ministerio de Ciencia e Innovación TEC2008-04920 y DPI2008-03847Junta de Andalucía P08-TIC-0367

Design methodology for FPGA implementation of lattice piecewise-affine functions

This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation of the problem, obtains the parameters required by a parameterized digital architecture, and ends with the bitstream to program an FPGA. The methodology has been proven to implement PWA functions on Xilinx FPGAs. The results are compared with other approaches for FPGA implementations of PWA function

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification

Physical Unclonable functions (PUFs) have appeared as a promising solution to provide security in hardware. SRAM PUFs offer the advantage, over other PUF constructions, of reusing resources (memories) that already exist in many designs. However, their intrinsic noisy nature produces the so called bit flipping effect, which is a problem in circuit identification and secret key generation. The approaches reported to reduce this effect usually resort to the use of pre- and post-processing steps (such as Fuzzy Extractor structures combined with Error Correcting Codes), which increase the complexity of the system. This paper proposes a pre-processing step that reduces bit flipping problems without increasing the hardware complexity. The proposal has been verified experimentally with 90-nm SRAMs included in digital application specific integrated circuits (ASICs).Junta de Andalucía P08-TIC-03674Ministerio de Economía y Competitividad TEC2011-24319Comunidad Europea FP7-INFSO-ICT-24885

ASIC-in-the-loop methodology for verification of piecewise affine controllers

This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations.Comunidad Europea FP7-INFSO-ICT-248858Gobierno Español TEC2011-24319Junta de Andalucía P08-TIC-0367